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| author | Tim Northover <tnorthover@apple.com> | 2014-04-03 15:10:35 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-03 15:10:35 +0000 |
| commit | d5561bb1f0fe5c67af59d79a6961ebf4b3c7b953 (patch) | |
| tree | d54caf5e1716ad65081e0c1059555564b5b9cd71 /lib | |
| parent | 769a6f211604f0285c419102846cfc91ab1e63cc (diff) | |
| download | llvm-d5561bb1f0fe5c67af59d79a6961ebf4b3c7b953.tar.gz llvm-d5561bb1f0fe5c67af59d79a6961ebf4b3c7b953.tar.bz2 llvm-d5561bb1f0fe5c67af59d79a6961ebf4b3c7b953.tar.xz | |
ARM: tell LLVM about zext properties of ldrexb/ldrexh
Implementing this via ComputeMaskedBits has two advantages:
+ It actually works. DAGISel doesn't deal with the chains properly
in the previous pattern-based solution, so they never trigger.
+ The information can be used in other DAG combines, as well as the
trivial "get rid of truncs". For example if the trunc is in a
different basic block.
rdar://problem/16227836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205540 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 |
2 files changed, 14 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 310d845db1..2ebad8e0e4 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -9964,6 +9964,20 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, KnownOne &= KnownOneRHS; return; } + case ISD::INTRINSIC_W_CHAIN: { + ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1)); + Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); + switch (IntID) { + default: return; + case Intrinsic::arm_ldaex: + case Intrinsic::arm_ldrex: { + EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); + unsigned MemBits = VT.getScalarType().getSizeInBits(); + KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits); + return; + } + } + } } } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 1f09c9f07d..75a109e2c3 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4476,19 +4476,11 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", let Inst{31-0} = 0b11110101011111111111000000011111; } -def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff), - (LDREXB addr_offset_none:$addr)>; -def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), - (LDREXH addr_offset_none:$addr)>; def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), (STREXB GPR:$Rt, addr_offset_none:$addr)>; def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), (STREXH GPR:$Rt, addr_offset_none:$addr)>; -def : ARMPat<(and (ldaex_1 addr_offset_none:$addr), 0xff), - (LDAEXB addr_offset_none:$addr)>; -def : ARMPat<(and (ldaex_2 addr_offset_none:$addr), 0xffff), - (LDAEXH addr_offset_none:$addr)>; def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), (STLEXB GPR:$Rt, addr_offset_none:$addr)>; def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), |