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author | Bill Wendling <isanbard@gmail.com> | 2013-06-19 20:32:16 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2013-06-19 20:32:16 +0000 |
commit | d626d33246c897a10d40e01b8658fa05c36b1e5f (patch) | |
tree | 03a58eaa456b0f273e7d3d604151de71ab728eda /lib | |
parent | c896020dd8d6c2f25f5bf7eb9191fd4e72407015 (diff) | |
download | llvm-d626d33246c897a10d40e01b8658fa05c36b1e5f.tar.gz llvm-d626d33246c897a10d40e01b8658fa05c36b1e5f.tar.bz2 llvm-d626d33246c897a10d40e01b8658fa05c36b1e5f.tar.xz |
Don't cache the TLI object since we have access to it through TargetMachine already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 86e188a007..2fb7664860 100644 --- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -55,15 +55,12 @@ static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { return false; } -FunctionLoweringInfo::FunctionLoweringInfo(const TargetMachine &TM) - : TM(TM), TLI(0) { -} - void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) { + const TargetLowering *TLI = TM.getTargetLowering(); + Fn = &fn; MF = &mf; RegInfo = &MF->getRegInfo(); - TLI = TM.getTargetLowering(); // Check whether the function can return without sret-demotion. SmallVector<ISD::OutputArg, 4> Outs; @@ -209,7 +206,8 @@ void FunctionLoweringInfo::clear() { /// CreateReg - Allocate a single virtual register for the given type. unsigned FunctionLoweringInfo::CreateReg(MVT VT) { - return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT)); + return RegInfo-> + createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT)); } /// CreateRegs - Allocate the appropriate number of virtual registers of @@ -220,6 +218,8 @@ unsigned FunctionLoweringInfo::CreateReg(MVT VT) { /// will assign registers for each member or element. /// unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) { + const TargetLowering *TLI = TM.getTargetLowering(); + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(*TLI, Ty, ValueVTs); @@ -267,6 +267,8 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { if (!Ty->isIntegerTy() || Ty->isVectorTy()) return; + const TargetLowering *TLI = TM.getTargetLowering(); + SmallVector<EVT, 1> ValueVTs; ComputeValueVTs(*TLI, Ty, ValueVTs); assert(ValueVTs.size() == 1 && |