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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-11-07 19:10:49 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-11-07 19:10:49 +0000 |
| commit | d83d98d4eb9595a88b830f5e3f5c6c24fae80df1 (patch) | |
| tree | 2fe483d264bcc39c908233a50463528b43e89167 /lib | |
| parent | f83ba3293fb6a3ef84483b5513e2e28af15e1222 (diff) | |
| download | llvm-d83d98d4eb9595a88b830f5e3f5c6c24fae80df1.tar.gz llvm-d83d98d4eb9595a88b830f5e3f5c6c24fae80df1.tar.bz2 llvm-d83d98d4eb9595a88b830f5e3f5c6c24fae80df1.tar.xz | |
Add definition of 64-bit load upper immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143994 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 1 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 6 |
2 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 1e8bf70242..9a769e8ac6 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -69,6 +69,7 @@ def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; +def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 64dbd26469..1cc3841352 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -334,8 +334,8 @@ class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, } // Load Upper Imediate -class LoadUpper<bits<6> op, string instr_asm>: - FI<op, (outs CPURegs:$rt), (ins uimm16:$imm16), +class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: + FI<op, (outs RC:$rt), (ins Imm:$imm16), !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { let rs = 0; } @@ -680,7 +680,7 @@ def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; -def LUi : LoadUpper<0x0f, "lui">; +def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; |