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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-02-10 14:24:23 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-02-10 14:24:23 +0000 |
| commit | dbd5c285b8a878ef068b6fb05f1981cf4878f0db (patch) | |
| tree | e2e04bd0f1cbedcddfdb1e5e534095626a673006 /lib | |
| parent | 299918ad4813ded5eb717c0c4898eb67205d880b (diff) | |
| download | llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.gz llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.bz2 llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.xz | |
ARM: r12 is callee-saved for interrupt handlers
For A- and R-class processors, r12 is not normally callee-saved, but is for
interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index e28fff68f4..4e72f6bd5b 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -42,7 +42,7 @@ static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { case R4: case R5: case R6: case R7: case LR: case SP: case PC: return true; - case R8: case R9: case R10: case R11: + case R8: case R9: case R10: case R11: case R12: // For iOS we want r7 and lr to be next to each other. return !isIOS; default: @@ -53,7 +53,7 @@ static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { using namespace ARM; switch (Reg) { - case R8: case R9: case R10: case R11: + case R8: case R9: case R10: case R11: case R12: // iOS has this second area. return isIOS; default: |