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| author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 19:55:55 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 19:55:55 +0000 |
| commit | e672ff84308434ad5517a5c6fc36e691893fca96 (patch) | |
| tree | bbb5ff9da6855462dccdbae88400ab700674b10e /lib | |
| parent | 6a44adade20bdea80c76b68833ec5eff5baaba98 (diff) | |
| download | llvm-e672ff84308434ad5517a5c6fc36e691893fca96.tar.gz llvm-e672ff84308434ad5517a5c6fc36e691893fca96.tar.bz2 llvm-e672ff84308434ad5517a5c6fc36e691893fca96.tar.xz | |
Properly pseudo-ize ARM MVNCCi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 16 |
2 files changed, 15 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 7e11263313..d221f30d9b 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -756,6 +756,17 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.eraseFromParent(); return true; } + case ARM::MVNCCi: { + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), + MI.getOperand(1).getReg()) + .addImm(MI.getOperand(2).getImm()) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addReg(MI.getOperand(4).getReg()) + .addReg(0); // 's' bit + + MI.eraseFromParent(); + return true; + } case ARM::Int_eh_sjlj_dispatchsetup: { MachineFunction &MF = *MI.getParent()->getParent(); const ARMBaseInstrInfo *AII = diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b6c447bb5c..9243e860e5 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3183,19 +3183,11 @@ def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd), Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">; let isMoveImm = 1 in -def MVNCCi : AI1<0b1111, (outs GPR:$Rd), - (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi, - "mvn", "\t$Rd, $imm", +def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), + (ins GPR:$false, so_imm:$imm, pred:$p), + Size4Bytes, IIC_iCMOVi, [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>, - RegConstraint<"$false = $Rd">, UnaryDP { - bits<4> Rd; - bits<12> imm; - let Inst{25} = 1; - let Inst{20} = 0; - let Inst{19-16} = 0b0000; - let Inst{15-12} = Rd; - let Inst{11-0} = imm; -} + RegConstraint<"$false = $Rd">; } // neverHasSideEffects //===----------------------------------------------------------------------===// |