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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-17 21:00:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-17 21:00:09 +0000 |
| commit | ec6e62ec98afe0397c006a4036dff57cccee163e (patch) | |
| tree | 5176c82f03840be04dc6073519272a1e4baae7a7 /lib | |
| parent | c2bab04829e32a078069a32152aed7885071eb5c (diff) | |
| download | llvm-ec6e62ec98afe0397c006a4036dff57cccee163e.tar.gz llvm-ec6e62ec98afe0397c006a4036dff57cccee163e.tar.bz2 llvm-ec6e62ec98afe0397c006a4036dff57cccee163e.tar.xz | |
R600/SI: Change default register class for i32 to SReg_32
SIFixSGPRCopies is smart enough to handle this now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206499 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 9d039ddcd2..1c7f5f00c4 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -35,7 +35,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); - addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass); + addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass); addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass); |