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| author | Tim Northover <tnorthover@apple.com> | 2013-12-11 16:04:57 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-12-11 16:04:57 +0000 |
| commit | ee06f15a0e1cebfeee2af9929f5b3afc94a78517 (patch) | |
| tree | 74d381877389f06f0f8e81aaf9bf37b95d56a823 /lib | |
| parent | 00a9489ff302c6c92689c96ebd7585a1a74edbea (diff) | |
| download | llvm-ee06f15a0e1cebfeee2af9929f5b3afc94a78517.tar.gz llvm-ee06f15a0e1cebfeee2af9929f5b3afc94a78517.tar.bz2 llvm-ee06f15a0e1cebfeee2af9929f5b3afc94a78517.tar.xz | |
ARM: constrain register-class in fast-isel
The tests were no longer using fast-isel at all (MachO needs an "ios" rather
than "darwin" triple at the moment and Linux needs ARM mode). Once that was
corrected, the verifier complained about a t2ADDri created for the alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197046 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 975417eba0..f696113b42 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -801,9 +801,11 @@ unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { // This will get lowered later into the correct offsets and registers // via rewriteXFrameIndex. if (SI != FuncInfo.StaticAllocaMap.end()) { + unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; const TargetRegisterClass* RC = TLI.getRegClassFor(VT); unsigned ResultReg = createResultReg(RC); - unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; + ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addFrameIndex(SI->second) |