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author | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-30 15:29:57 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-30 15:29:57 +0000 |
commit | fa2e88da1c8b8d98c2f0ffeba963f0eaa3a18e9c (patch) | |
tree | 6cbb871d31a0a9cf234ede20e248bbf2cfa2234c /lib | |
parent | 3dbcd2e69eabb390c45a86d35b911d1d4d756e20 (diff) | |
download | llvm-fa2e88da1c8b8d98c2f0ffeba963f0eaa3a18e9c.tar.gz llvm-fa2e88da1c8b8d98c2f0ffeba963f0eaa3a18e9c.tar.bz2 llvm-fa2e88da1c8b8d98c2f0ffeba963f0eaa3a18e9c.tar.xz |
[ARM64][fast-isel] Fast-isel doesn't know how to handle f128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207659 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM64/ARM64FastISel.cpp | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/lib/Target/ARM64/ARM64FastISel.cpp b/lib/Target/ARM64/ARM64FastISel.cpp index 0fce1cc64e..c43f2af15b 100644 --- a/lib/Target/ARM64/ARM64FastISel.cpp +++ b/lib/Target/ARM64/ARM64FastISel.cpp @@ -197,6 +197,9 @@ unsigned ARM64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) { } unsigned ARM64FastISel::ARM64MaterializeFP(const ConstantFP *CFP, MVT VT) { + if (VT != MVT::f32 && VT != MVT::f64) + return 0; + const APFloat Val = CFP->getValueAPF(); bool is64bit = (VT == MVT::f64); @@ -418,7 +421,11 @@ bool ARM64FastISel::isTypeLegal(Type *Ty, MVT &VT) { return false; VT = evt.getSimpleVT(); - // Handle all legal types, i.e. a register that will directly hold this + // This is a legal type, but it's not something we handle in fast-isel. + if (VT == MVT::f128) + return false; + + // Handle all other legal types, i.e. a register that will directly hold this // value. return TLI.isTypeLegal(VT); } @@ -1107,6 +1114,8 @@ bool ARM64FastISel::SelectFPToInt(const Instruction *I, bool Signed) { return false; EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true); + if (SrcVT == MVT::f128) + return false; unsigned Opc; if (SrcVT == MVT::f64) { @@ -1132,6 +1141,8 @@ bool ARM64FastISel::SelectIntToFP(const Instruction *I, bool Signed) { MVT DestVT; if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) return false; + assert ((DestVT == MVT::f32 || DestVT == MVT::f64) && + "Unexpected value type."); unsigned SrcReg = getRegForValue(I->getOperand(0)); if (SrcReg == 0) @@ -1578,6 +1589,8 @@ bool ARM64FastISel::SelectRet(const Instruction *I) { if (!RVEVT.isSimple()) return false; MVT RVVT = RVEVT.getSimpleVT(); + if (RVVT == MVT::f128) + return false; MVT DestVT = VA.getValVT(); // Special handling for extended integers. if (RVVT != DestVT) { |