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| author | Owen Anderson <resistor@mac.com> | 2010-12-09 21:34:47 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-12-09 21:34:47 +0000 |
| commit | fe7fac74b4edaf9cc04460fc21aa949e5533aea2 (patch) | |
| tree | eee103f45af4b1803dd3602e9b6fc97b6d1d1da3 /lib | |
| parent | a304d02791b3e0297a9d545e0c602c9f916691f9 (diff) | |
| download | llvm-fe7fac74b4edaf9cc04460fc21aa949e5533aea2.tar.gz llvm-fe7fac74b4edaf9cc04460fc21aa949e5533aea2.tar.bz2 llvm-fe7fac74b4edaf9cc04460fc21aa949e5533aea2.tar.xz | |
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
but it gets many more of them correct than it did previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121414 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMAsmBackend.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMAsmBackend.cpp b/lib/Target/ARM/ARMAsmBackend.cpp index 606437efbb..7311b4181d 100644 --- a/lib/Target/ARM/ARMAsmBackend.cpp +++ b/lib/Target/ARM/ARMAsmBackend.cpp @@ -101,6 +101,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { case ARM::fixup_arm_ldst_pcrel_12: // ARM PC-relative values are offset by 8. Value -= 4; + // FALLTHROUGH case ARM::fixup_t2_ldst_pcrel_12: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. Value -= 4; @@ -140,7 +141,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // Offset by 8 just as above. return 0xffffff & ((Value - 8) >> 2); case ARM::fixup_t2_branch: { - Value = Value - 8; + Value = Value - 6; Value >>= 1; // Low bit is not encoded. uint64_t out = 0; diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 4d8791c998..c901831d85 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -53,7 +53,8 @@ public: { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, |