AArch64: The pattern match should check the range of the immediate value.

Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195941 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 8 deletions

diff --git a/test/CodeGen/AArch64/neon-scalar-cvt.ll b/test/CodeGen/AArch64/neon-scalar-cvt.ll
index 2fe25b8c19..a06d5d60a8 100644
--- a/test/CodeGen/AArch64/neon-scalar-cvt.ll
+++ b/test/CodeGen/AArch64/neon-scalar-cvt.ll
@@ -90,10 +90,10 @@ declare double @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32)
 
 define i32 @test_vcvts_n_s32_f32(float %a) {
 ; CHECK: test_vcvts_n_s32_f32
-; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #0
+; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
 entry:
   %fcvtzs = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 0)
+  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 1)
   %0 = extractelement <1 x i32> %fcvtzs1, i32 0
   ret i32 %0
 }
@@ -102,10 +102,10 @@ declare <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float>, i32)
 
 define i64 @test_vcvtd_n_s64_f64(double %a) {
 ; CHECK: test_vcvtd_n_s64_f64
-; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #0
+; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
 entry:
   %fcvtzs = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 0)
+  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 1)
   %0 = extractelement <1 x i64> %fcvtzs1, i32 0
   ret i64 %0
 }
@@ -114,10 +114,10 @@ declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double>, i32)
 
 define i32 @test_vcvts_n_u32_f32(float %a) {
 ; CHECK: test_vcvts_n_u32_f32
-; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #0
+; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
 entry:
   %fcvtzu = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 0)
+  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 32)
   %0 = extractelement <1 x i32> %fcvtzu1, i32 0
   ret i32 %0
 }
@@ -126,10 +126,10 @@ declare <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float>, i32)
 
 define i64 @test_vcvtd_n_u64_f64(double %a) {
 ; CHECK: test_vcvtd_n_u64_f64
-; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #0
+; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
 entry:
   %fcvtzu = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 0)
+  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 64)
   %0 = extractelement <1 x i64> %fcvtzu1, i32 0
   ret i64 %0
 }