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author | Tim Northover <tnorthover@apple.com> | 2014-04-24 14:06:20 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-04-24 14:06:20 +0000 |
commit | a05d37e1f425c1f83fa38d069957da83b7ac54d4 (patch) | |
tree | fcea3a001ddef255ea87185c775ae8932e1f827b /test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll | |
parent | 23a4885f59511eb4781e534a3b2a5910733cb357 (diff) | |
download | llvm-a05d37e1f425c1f83fa38d069957da83b7ac54d4.tar.gz llvm-a05d37e1f425c1f83fa38d069957da83b7ac54d4.tar.bz2 llvm-a05d37e1f425c1f83fa38d069957da83b7ac54d4.tar.xz |
AArch64: print NEON lists with a space.
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll')
-rw-r--r-- | test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll b/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll index 2e3f7bff02..60cc6e40b3 100644 --- a/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll +++ b/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll @@ -9,14 +9,14 @@ define <16 x i8> @qwordint (<16 x i8>* %head.v16i8, <8 x i16>* %head.v8i16, <4 x i32>* %head.v4i32, <2 x i64>* %head.v2i64, <16 x i8>* %tail.v16i8, <8 x i16>* %tail.v8i16, <4 x i32>* %tail.v4i32, <2 x i64>* %tail.v2i64) { ; CHECK-LABEL: qwordint -; CHECK: ld1 {v0.16b}, [x0] -; CHECK: ld1 {v1.8h}, [x1] -; CHECK: ld1 {v2.4s}, [x2] -; CHECK: ld1 {v3.2d}, [x3] -; CHECK: st1 {v0.16b}, [x4] -; CHECK: st1 {v1.8h}, [x5] -; CHECK: st1 {v2.4s}, [x6] -; CHECK: st1 {v3.2d}, [x7] +; CHECK: ld1 { v0.16b }, [x0] +; CHECK: ld1 { v1.8h }, [x1] +; CHECK: ld1 { v2.4s }, [x2] +; CHECK: ld1 { v3.2d }, [x3] +; CHECK: st1 { v0.16b }, [x4] +; CHECK: st1 { v1.8h }, [x5] +; CHECK: st1 { v2.4s }, [x6] +; CHECK: st1 { v3.2d }, [x7] ; BE-STRICT-ALIGN-LABEL: qwordint ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh @@ -42,10 +42,10 @@ entry: define <4 x float> @qwordfloat (<4 x float>* %head.v4f32, <2 x double>* %head.v2f64, <4 x float>* %tail.v4f32, <2 x double>* %tail.v2f64) { ; CHECK-LABEL: qwordfloat -; CHECK: ld1 {v0.4s}, [x0] -; CHECK: ld1 {v1.2d}, [x1] -; CHECK: st1 {v0.4s}, [x2] -; CHECK: st1 {v1.2d}, [x3] +; CHECK: ld1 { v0.4s }, [x0] +; CHECK: ld1 { v1.2d }, [x1] +; CHECK: st1 { v0.4s }, [x2] +; CHECK: st1 { v1.2d }, [x3] ; BE-STRICT-ALIGN-LABEL: qwordfloat ; BE-STRICT-ALIGN: ldr ; BE-STRICT-ALIGN: ldr @@ -63,23 +63,23 @@ entry: define <8 x i8> @dwordint (<8 x i8>* %head.v8i8, <4 x i16>* %head.v4i16, <2 x i32>* %head.v2i32, <1 x i64>* %head.v1i64, <8 x i8>* %tail.v8i8, <4 x i16>* %tail.v4i16, <2 x i32>* %tail.v2i32, <1 x i64>* %tail.v1i64) { ; CHECK-LABEL: dwordint -; CHECK: ld1 {v0.8b}, [x0] -; CHECK: ld1 {v1.4h}, [x1] -; CHECK: ld1 {v2.2s}, [x2] -; CHECK: ld1 {v3.1d}, [x3] -; CHECK: st1 {v0.8b}, [x4] -; CHECK: st1 {v1.4h}, [x5] -; CHECK: st1 {v2.2s}, [x6] -; CHECK: st1 {v3.1d}, [x7] +; CHECK: ld1 { v0.8b }, [x0] +; CHECK: ld1 { v1.4h }, [x1] +; CHECK: ld1 { v2.2s }, [x2] +; CHECK: ld1 { v3.1d }, [x3] +; CHECK: st1 { v0.8b }, [x4] +; CHECK: st1 { v1.4h }, [x5] +; CHECK: st1 { v2.2s }, [x6] +; CHECK: st1 { v3.1d }, [x7] ; BE-STRICT-ALIGN-LABEL: dwordint ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh ; BE-STRICT-ALIGN: ldr -; BE-STRICT-ALIGN: ld1 {v1.1d}, [x3] +; BE-STRICT-ALIGN: ld1 { v1.1d }, [x3] ; BE-STRICT-ALIGN: strb ; BE-STRICT-ALIGN: strh ; BE-STRICT-ALIGN: str -; BE-STRICT-ALIGN: st1 {v1.1d}, [x7] +; BE-STRICT-ALIGN: st1 { v1.1d }, [x7] entry: %val.v8i8 = load <8 x i8>* %head.v8i8, align 1 %val.v4i16 = load <4 x i16>* %head.v4i16, align 2 @@ -96,15 +96,15 @@ entry: define <2 x float> @dwordfloat (<2 x float>* %head.v2f32, <1 x double>* %head.v1f64, <2 x float>* %tail.v2f32, <1 x double>* %tail.v1f64) { ; CHECK-LABEL: dwordfloat -; CHECK: ld1 {v0.2s}, [x0] -; CHECK: ld1 {v1.1d}, [x1] -; CHECK: st1 {v0.2s}, [x2] -; CHECK: st1 {v1.1d}, [x3] +; CHECK: ld1 { v0.2s }, [x0] +; CHECK: ld1 { v1.1d }, [x1] +; CHECK: st1 { v0.2s }, [x2] +; CHECK: st1 { v1.1d }, [x3] ; BE-STRICT-ALIGN-LABEL: dwordfloat ; BE-STRICT-ALIGN: ldr -; BE-STRICT-ALIGN: ld1 {v1.1d}, [x1] +; BE-STRICT-ALIGN: ld1 { v1.1d }, [x1] ; BE-STRICT-ALIGN: str -; BE-STRICT-ALIGN: st1 {v1.1d}, [x3] +; BE-STRICT-ALIGN: st1 { v1.1d }, [x3] entry: %val.v2f32 = load <2 x float>* %head.v2f32, align 4 %val.v1f64 = load <1 x double>* %head.v1f64, align 8 @@ -117,14 +117,14 @@ entry: define <2 x i64> @align2vi64 (<2 x i64>* %head.byte, <2 x i64>* %head.half, <2 x i64>* %head.word, <2 x i64>* %head.dword, <2 x i64>* %tail.byte, <2 x i64>* %tail.half, <2 x i64>* %tail.word, <2 x i64>* %tail.dword) { ; CHECK-LABEL: align2vi64 -; CHECK: ld1 {v0.2d}, [x0] -; CHECK: ld1 {v1.2d}, [x1] -; CHECK: ld1 {v2.2d}, [x2] -; CHECK: ld1 {v3.2d}, [x3] -; CHECK: st1 {v0.2d}, [x4] -; CHECK: st1 {v1.2d}, [x5] -; CHECK: st1 {v2.2d}, [x6] -; CHECK: st1 {v3.2d}, [x7] +; CHECK: ld1 { v0.2d }, [x0] +; CHECK: ld1 { v1.2d }, [x1] +; CHECK: ld1 { v2.2d }, [x2] +; CHECK: ld1 { v3.2d }, [x3] +; CHECK: st1 { v0.2d }, [x4] +; CHECK: st1 { v1.2d }, [x5] +; CHECK: st1 { v2.2d }, [x6] +; CHECK: st1 { v3.2d }, [x7] ; BE-STRICT-ALIGN-LABEL: align2vi64 ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh @@ -142,18 +142,18 @@ entry: store <2 x i64> %val.word, <2 x i64>* %tail.word, align 4 store <2 x i64> %val.dword, <2 x i64>* %tail.dword, align 8 ret <2 x i64> %val.byte -} + } ;; Check load/store of 64-bit vectors with less-than 8-byte alignment define <2 x float> @align2vf32 (<2 x float>* %head.byte, <2 x float>* %head.half, <2 x float>* %head.word, <2 x float>* %head.dword, <2 x float>* %tail.byte, <2 x float>* %tail.half, <2 x float>* %tail.word, <2 x float>* %tail.dword) { ; CHECK-LABEL: align2vf32 -; CHECK: ld1 {v0.2s}, [x0] -; CHECK: ld1 {v1.2s}, [x1] -; CHECK: ld1 {v2.2s}, [x2] -; CHECK: st1 {v0.2s}, [x4] -; CHECK: st1 {v1.2s}, [x5] -; CHECK: st1 {v2.2s}, [x6] +; CHECK: ld1 { v0.2s }, [x0] +; CHECK: ld1 { v1.2s }, [x1] +; CHECK: ld1 { v2.2s }, [x2] +; CHECK: st1 { v0.2s }, [x4] +; CHECK: st1 { v1.2s }, [x5] +; CHECK: st1 { v2.2s }, [x6] ; BE-STRICT-ALIGN-LABEL: align2vf32 ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh |