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authorChad Rosier <mcrosier@codeaurora.org>2014-06-09 01:54:00 +0000
committerChad Rosier <mcrosier@codeaurora.org>2014-06-09 01:54:00 +0000
commit451cc566c10b1e057ad8b3c1d1308e8f4b6fb685 (patch)
treeb3b6921728f22ae1d986d012af94af7623a3723f /test/CodeGen/AArch64
parent0607e82c0a59491a5b27ec150ac1c77345ecea6a (diff)
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[AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
-rw-r--r--test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll7
1 files changed, 4 insertions, 3 deletions
diff --git a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
index 97bfb5ca9d..07373ccedc 100644
--- a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
+++ b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
@@ -6,9 +6,10 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: shiftable
-; CHECK: *** Final schedule for BB#0 ***
-; CHECK: ADDXrr %vreg0, %vreg2
-; CHECK: ADDXrs %vreg0, %vreg2, 5
+; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
+; CHECK: Successors:
+; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
+; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
; CHECK: ********** INTERVALS **********
define i64 @shiftable(i64 %A, i64 %B) {
%tmp0 = sub i64 %B, 20