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author | Tim Northover <tnorthover@apple.com> | 2014-04-15 14:00:19 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-04-15 14:00:19 +0000 |
commit | 5f8234943d84112caad08d5bb4886f0aecffbd87 (patch) | |
tree | eef4351aef3c483be26e5425a02195d039bc366d /test/CodeGen/AArch64 | |
parent | 2a83cb71ad74988d834c8969ca34027fce251a12 (diff) | |
download | llvm-5f8234943d84112caad08d5bb4886f0aecffbd87.tar.gz llvm-5f8234943d84112caad08d5bb4886f0aecffbd87.tar.bz2 llvm-5f8234943d84112caad08d5bb4886f0aecffbd87.tar.xz |
AArch64/ARM64: add missing pattern for extending load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206290 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
-rw-r--r-- | test/CodeGen/AArch64/ldst-regoffset.ll | 79 |
1 files changed, 40 insertions, 39 deletions
diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll index db30fd915f..ca4e8ac293 100644 --- a/test/CodeGen/AArch64/ldst-regoffset.ll +++ b/test/CodeGen/AArch64/ldst-regoffset.ll @@ -1,5 +1,6 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-none-linux-gnu | FileCheck %s @var_8bit = global i8 0 @var_16bit = global i16 0 @@ -9,14 +10,14 @@ @var_float = global float 0.0 @var_double = global double 0.0 -define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) { +define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_8bit: %addr8_sxtw = getelementptr i8* %base, i32 %off32 %val8_sxtw = load volatile i8* %addr8_sxtw %val32_signed = sext i8 %val8_sxtw to i32 store volatile i32 %val32_signed, i32* @var_32bit -; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] %addr_lsl = getelementptr i8* %base, i64 %off64 %val8_lsl = load volatile i8* %addr_lsl @@ -31,20 +32,20 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) { %val8_uxtw = load volatile i8* %addr_uxtw %newval8 = add i8 %val8_uxtw, 1 store volatile i8 %newval8, i8* @var_8bit -; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ret void } -define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { +define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_16bit: %addr8_sxtwN = getelementptr i16* %base, i32 %off32 %val8_sxtwN = load volatile i16* %addr8_sxtwN %val32_signed = sext i16 %val8_sxtwN to i32 store volatile i32 %val32_signed, i32* @var_32bit -; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #1] +; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1] %addr_lslN = getelementptr i16* %base, i64 %off64 %val8_lslN = load volatile i16* %addr_lslN @@ -59,7 +60,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { %val8_uxtw = load volatile i16* %addr_uxtw %newval8 = add i16 %val8_uxtw, 1 store volatile i16 %newval8, i16* @var_16bit -; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] %base_sxtw = ptrtoint i16* %base to i64 %offset_sxtw = sext i32 %off32 to i64 @@ -68,7 +69,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { %val16_sxtw = load volatile i16* %addr_sxtw %val64_signed = sext i16 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit -; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] %base_lsl = ptrtoint i16* %base to i64 @@ -87,17 +88,17 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { %val32 = load volatile i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* %addr_uxtwN -; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1] ret void } -define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { +define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_32bit: %addr_sxtwN = getelementptr i32* %base, i32 %off32 %val_sxtwN = load volatile i32* %addr_sxtwN store volatile i32 %val_sxtwN, i32* @var_32bit -; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #2] +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] %addr_lslN = getelementptr i32* %base, i64 %off64 %val_lslN = load volatile i32* %addr_lslN @@ -111,7 +112,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { %val_uxtw = load volatile i32* %addr_uxtw %newval8 = add i32 %val_uxtw, 1 store volatile i32 %newval8, i32* @var_32bit -; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] %base_sxtw = ptrtoint i32* %base to i64 @@ -121,7 +122,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { %val16_sxtw = load volatile i32* %addr_sxtw %val64_signed = sext i32 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit -; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] %base_lsl = ptrtoint i32* %base to i64 @@ -139,17 +140,17 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32* %val32 = load volatile i32* @var_32bit store volatile i32 %val32, i32* %addr_uxtwN -; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] ret void } -define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { +define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_64bit: %addr_sxtwN = getelementptr i64* %base, i32 %off32 %val_sxtwN = load volatile i64* %addr_sxtwN store volatile i64 %val_sxtwN, i64* @var_64bit -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #3] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3] %addr_lslN = getelementptr i64* %base, i64 %off64 %val_lslN = load volatile i64* %addr_lslN @@ -163,7 +164,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { %val8_uxtw = load volatile i64* %addr_uxtw %newval8 = add i64 %val8_uxtw, 1 store volatile i64 %newval8, i64* @var_64bit -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] %base_sxtw = ptrtoint i64* %base to i64 %offset_sxtw = sext i32 %off32 to i64 @@ -171,7 +172,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { %addr_sxtw = inttoptr i64 %addrint_sxtw to i64* %val64_sxtw = load volatile i64* %addr_sxtw store volatile i64 %val64_sxtw, i64* @var_64bit -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] %base_lsl = ptrtoint i64* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 @@ -187,17 +188,17 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64* %val64 = load volatile i64* @var_64bit store volatile i64 %val64, i64* %addr_uxtwN -; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] ret void } -define void @ldst_float(float* %base, i32 %off32, i64 %off64) { +define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_float: %addr_sxtwN = getelementptr float* %base, i32 %off32 %val_sxtwN = load volatile float* %addr_sxtwN store volatile float %val_sxtwN, float* @var_float -; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #2] +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, %addr_lslN = getelementptr float* %base, i64 %off64 @@ -212,7 +213,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) { %addr_uxtw = inttoptr i64 %addrint1_uxtw to float* %val_uxtw = load volatile float* %addr_uxtw store volatile float %val_uxtw, float* @var_float -; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, %base_sxtw = ptrtoint float* %base to i64 @@ -221,7 +222,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) { %addr_sxtw = inttoptr i64 %addrint_sxtw to float* %val64_sxtw = load volatile float* %addr_sxtw store volatile float %val64_sxtw, float* @var_float -; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, %base_lsl = ptrtoint float* %base to i64 @@ -239,18 +240,18 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) { %addr_uxtwN = inttoptr i64 %addrint_uxtwN to float* %val64 = load volatile float* @var_float store volatile float %val64, float* %addr_uxtwN -; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] +; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, ret void } -define void @ldst_double(double* %base, i32 %off32, i64 %off64) { +define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_double: %addr_sxtwN = getelementptr double* %base, i32 %off32 %val_sxtwN = load volatile double* %addr_sxtwN store volatile double %val_sxtwN, double* @var_double -; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #3] +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, %addr_lslN = getelementptr double* %base, i64 %off64 @@ -265,7 +266,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) { %addr_uxtw = inttoptr i64 %addrint1_uxtw to double* %val_uxtw = load volatile double* %addr_uxtw store volatile double %val_uxtw, double* @var_double -; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, %base_sxtw = ptrtoint double* %base to i64 @@ -274,7 +275,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) { %addr_sxtw = inttoptr i64 %addrint_sxtw to double* %val64_sxtw = load volatile double* %addr_sxtw store volatile double %val64_sxtw, double* @var_double -; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, %base_lsl = ptrtoint double* %base to i64 @@ -292,26 +293,26 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) { %addr_uxtwN = inttoptr i64 %addrint_uxtwN to double* %val64 = load volatile double* @var_double store volatile double %val64, double* %addr_uxtwN -; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] +; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, ret void } -define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { +define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_128bit: %addr_sxtwN = getelementptr fp128* %base, i32 %off32 %val_sxtwN = load volatile fp128* %addr_sxtwN store volatile fp128 %val_sxtwN, fp128* %base -; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] %addr_lslN = getelementptr fp128* %base, i64 %off64 %val_lslN = load volatile fp128* %addr_lslN store volatile fp128 %val_lslN, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #4] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] %addrint_uxtw = ptrtoint fp128* %base to i64 %offset_uxtw = zext i32 %off32 to i64 @@ -319,8 +320,8 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { %addr_uxtw = inttoptr i64 %addrint1_uxtw to fp128* %val_uxtw = load volatile fp128* %addr_uxtw store volatile fp128 %val_uxtw, fp128* %base -; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] %base_sxtw = ptrtoint fp128* %base to i64 %offset_sxtw = sext i32 %off32 to i64 @@ -328,8 +329,8 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { %addr_sxtw = inttoptr i64 %addrint_sxtw to fp128* %val64_sxtw = load volatile fp128* %addr_sxtw store volatile fp128 %val64_sxtw, fp128* %base -; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] %base_lsl = ptrtoint fp128* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 @@ -337,7 +338,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { %val64_lsl = load volatile fp128* %addr_lsl store volatile fp128 %val64_lsl, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] %base_uxtwN = ptrtoint fp128* %base to i64 %offset_uxtwN = zext i32 %off32 to i64 @@ -346,7 +347,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { %addr_uxtwN = inttoptr i64 %addrint_uxtwN to fp128* %val64 = load volatile fp128* %base store volatile fp128 %val64, fp128* %addr_uxtwN -; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #4] -; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw #4] +; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #4] +; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] ret void } |