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| author | Andrew Trick <atrick@apple.com> | 2012-02-10 04:10:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-10 04:10:36 +0000 |
| commit | 8dd26253f54247e77e5accfdd70e7b4bf27b39c2 (patch) | |
| tree | df14b7b3cec3b603bc5feb7070a05f00eb83d4a5 /test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll | |
| parent | 16f72dd68653bd4984363483cfc15ce91fa613d4 (diff) | |
| download | llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.tar.gz llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.tar.bz2 llvm-8dd26253f54247e77e5accfdd70e7b4bf27b39c2.tar.xz | |
RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline.
Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
CodeGen transformation passes are never "required" as an analysis
ProcessImplicitDefs does not require LiveVariables.
We have a plan to massively simplify some of the early passes within the regalloc superpass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll')
| -rw-r--r-- | test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index a65cf4b5e6..e0f50c97ba 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=basic +; RUN: llc < %s -march=arm -mattr=+neon -O0 -optimize-regalloc -regalloc=basic ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. |