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| author | Bob Wilson <bob.wilson@apple.com> | 2010-10-08 06:15:13 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-10-08 06:15:13 +0000 |
| commit | 7d24705f6538688937f571961d41c7bb2985c7e3 (patch) | |
| tree | 5d387b68a25a6bebf6076c21a122b512674f628b /test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll | |
| parent | 40755467393f4569200cbc1cf1e9feeea4668611 (diff) | |
| download | llvm-7d24705f6538688937f571961d41c7bb2985c7e3.tar.gz llvm-7d24705f6538688937f571961d41c7bb2985c7e3.tar.bz2 llvm-7d24705f6538688937f571961d41c7bb2985c7e3.tar.xz | |
Change register allocation order for ARM VFP and NEON registers to put the
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll')
| -rw-r--r-- | test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index ffc47ebdf1..b9d5600d2a 100644 --- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -10,9 +10,9 @@ target triple = "thumbv7-apple-darwin10" ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial ; redef, it cannot also get %Q0. -; CHECK: vld1.64 {d0, d1}, [r{{.}}] -; CHECK-NOT: vld1.64 {d0, d1} -; CHECK: vmov.f64 d3, d0 +; CHECK: vld1.64 {d16, d17}, [r{{.}}] +; CHECK-NOT: vld1.64 {d16, d17} +; CHECK: vmov.f64 d19, d16 define i32 @test(i8* %arg) nounwind { entry: |