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authorJim Grosbach <grosbach@apple.com>2011-08-19 23:10:31 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-19 23:10:31 +0000
commita17f669ef56022a9fdab4689ef20f64a2667ea83 (patch)
treea3b88ce8e213f5d3c4ceaeee1d9ee6b9c073a62e /test/CodeGen/ARM/avoid-cpsr-rmw.ll
parent0e7128894337202ae4f368c0b14ce5909dddb84d (diff)
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Use regex to remove false dependencies on register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138137 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/avoid-cpsr-rmw.ll')
-rw-r--r--test/CodeGen/ARM/avoid-cpsr-rmw.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index d148bbe41f..92aff7007f 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -6,9 +6,9 @@
define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
; CHECK: t:
-; CHECK: muls r2, r2, r3
-; CHECK-NEXT: mul r0, r0, r1
-; CHECK-NEXT: muls r0, r0, r2
+; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
+; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1
+; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
%0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1