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authorJim Grosbach <grosbach@apple.com>2012-02-24 00:33:36 +0000
committerJim Grosbach <grosbach@apple.com>2012-02-24 00:33:36 +0000
commitfdf7c850321bba542e181ae035507d9c71d95364 (patch)
tree2d183d4f63fe14751bb3615a11b88eb0ea8bc3b2 /test/CodeGen/ARM/avoid-cpsr-rmw.ll
parent4bf6c19e94e4c7eb888d94c1aa322d23dbcc93ba (diff)
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Thumb2 size reduction fix for tied operands of tMUL.
The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151315 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/avoid-cpsr-rmw.ll')
-rw-r--r--test/CodeGen/ARM/avoid-cpsr-rmw.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index 877ec18062..1b385ab79c 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -6,9 +6,9 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
; CHECK: t1:
-; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
-; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1
-; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
+; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
+; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
+; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
%0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1