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| author | JF Bastien <jfb@google.com> | 2013-06-07 20:10:37 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-06-07 20:10:37 +0000 |
| commit | 8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3 (patch) | |
| tree | dcecbe4ed5eb38c277f470c5ecbdbad3ff116f2b /test/CodeGen/ARM/fast-isel-fold.ll | |
| parent | 1983a4cbf112c4f97fb332a4068aa42a9284cad1 (diff) | |
| download | llvm-8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3.tar.gz llvm-8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3.tar.bz2 llvm-8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3.tar.xz | |
ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.
The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.
fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).
2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.
fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.
Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.
I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-fold.ll')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-fold.ll | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-fold.ll b/test/CodeGen/ARM/fast-isel-fold.ll index 7a65295f01..c920f9b5e7 100644 --- a/test/CodeGen/ARM/fast-isel-fold.ll +++ b/test/CodeGen/ARM/fast-isel-fold.ll @@ -8,9 +8,11 @@ define void @t1() nounwind uwtable ssp { ; ARM: t1 ; ARM: ldrb ; ARM-NOT: uxtb +; ARM-NOT: and{{.*}}, #255 ; THUMB: t1 ; THUMB: ldrb ; THUMB-NOT: uxtb +; THUMB-NOT: and{{.*}}, #255 %1 = load i8* @a, align 1 call void @foo1(i8 zeroext %1) ret void @@ -35,9 +37,11 @@ define i32 @t3() nounwind uwtable ssp { ; ARM: t3 ; ARM: ldrb ; ARM-NOT: uxtb +; ARM-NOT: and{{.*}}, #255 ; THUMB: t3 ; THUMB: ldrb ; THUMB-NOT: uxtb +; THUMB-NOT: and{{.*}}, #255 %1 = load i8* @a, align 1 %2 = zext i8 %1 to i32 ret i32 %2 |