diff options
| author | Andrew Trick <atrick@apple.com> | 2011-04-12 19:54:36 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-12 19:54:36 +0000 |
| commit | 3eb4319313b3fb9189cd4be5b3e5375be9bdc2f9 (patch) | |
| tree | c789be1296f5462ce82ff1934f405a8a1302db38 /test/CodeGen/ARM/memcpy-inline.ll | |
| parent | 23ba1e4faa8317e762eb95aecd786e9600e9f834 (diff) | |
| download | llvm-3eb4319313b3fb9189cd4be5b3e5375be9bdc2f9.tar.gz llvm-3eb4319313b3fb9189cd4be5b3e5375be9bdc2f9.tar.bz2 llvm-3eb4319313b3fb9189cd4be5b3e5375be9bdc2f9.tar.xz | |
PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make these heuristic adjustments to node latency work,
I also needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129383 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/memcpy-inline.ll')
| -rw-r--r-- | test/CodeGen/ARM/memcpy-inline.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index e8a2a3b7d5..5bae037caf 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s ; The ARM magic hinting works best with linear scan. -; CHECK: ldmia -; CHECK: stmia -; CHECK: ldrh +; CHECK: ldrd +; CHECK: strd ; CHECK: ldrb %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } |