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author | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
commit | 5bafff36c798608a189c517d37527e4a38863071 (patch) | |
tree | 79bd2abbc5253e6f00db07023cf7d829cbcdee5a /test/CodeGen/ARM/neon_ld1.ll | |
parent | 5de83afcdc3f4f0edf8caacba523f5d05ee48048 (diff) | |
download | llvm-5bafff36c798608a189c517d37527e4a38863071.tar.gz llvm-5bafff36c798608a189c517d37527e4a38863071.tar.bz2 llvm-5bafff36c798608a189c517d37527e4a38863071.tar.xz |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/neon_ld1.ll')
-rw-r--r-- | test/CodeGen/ARM/neon_ld1.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/neon_ld1.ll b/test/CodeGen/ARM/neon_ld1.ll new file mode 100644 index 0000000000..8901ba177d --- /dev/null +++ b/test/CodeGen/ARM/neon_ld1.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fldd | count 4 +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fstd +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd + +define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind { +entry: + %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] + %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] + store <2 x i32> %3, <2 x i32>* %r, align 8 + ret void +} + +define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly { +entry: + %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] + %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] + ret <2 x i32> %3 +} |