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authorJim Grosbach <grosbach@apple.com>2010-12-09 18:31:13 +0000
committerJim Grosbach <grosbach@apple.com>2010-12-09 18:31:13 +0000
commitc6f9261711ac6666db5d99715531a41c1b1d98ed (patch)
treeab0f87e85d9fa3e4ac9927f1ce40e19ffdf32a80 /test/CodeGen/ARM/str_pre-2.ll
parent0e1fb7afcccb3ade0f159172e32292349f65011e (diff)
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ARM stm/ldm instructions require more than one register in the register list.
Otherwise, a plain str/ldr should be used instead. Make sure we account for that in prologue/epilogue code generation. rdar://8745460 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/str_pre-2.ll')
-rw-r--r--test/CodeGen/ARM/str_pre-2.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll
index a79cf9bf7f..4f9ba4db4c 100644
--- a/test/CodeGen/ARM/str_pre-2.ll
+++ b/test/CodeGen/ARM/str_pre-2.ll
@@ -4,8 +4,8 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
-; CHECK: push {lr}
-; CHECK: ldmia sp!, {pc}
+; CHECK: str lr, [sp, #-4]!
+; CHECK: ldr lr, [sp], #4
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a