summaryrefslogtreecommitdiff
path: root/test/CodeGen/ARM/vector-extend-narrow.ll
diff options
context:
space:
mode:
authorJames Molloy <james.molloy@arm.com>2012-04-05 10:01:12 +0000
committerJames Molloy <james.molloy@arm.com>2012-04-05 10:01:12 +0000
commit17dcaf5ef9e761bd3b516a3f4cb85a9fdcb5975e (patch)
tree3dd37f9b7c7221cdb5d4e791a0902da55ed52c08 /test/CodeGen/ARM/vector-extend-narrow.ll
parent87825e7970a361ce5a8bab19bc880ff7f6242ca2 (diff)
downloadllvm-17dcaf5ef9e761bd3b516a3f4cb85a9fdcb5975e.tar.gz
llvm-17dcaf5ef9e761bd3b516a3f4cb85a9fdcb5975e.tar.bz2
llvm-17dcaf5ef9e761bd3b516a3f4cb85a9fdcb5975e.tar.xz
An oversight when applying the patches for r150956 and r150957 to a vanilla tree meant I forgot to svn add these testcases.
Noticed while investigating PR12274! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vector-extend-narrow.ll')
-rw-r--r--test/CodeGen/ARM/vector-extend-narrow.ll46
1 files changed, 46 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
new file mode 100644
index 0000000000..5e9239f256
--- /dev/null
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -0,0 +1,46 @@
+; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
+
+; CHECK: f:
+define float @f(<4 x i16>* nocapture %in) {
+ ; CHECK: vldr
+ ; CHECK: vmovl.u16
+ %1 = load <4 x i16>* %in
+ ; CHECK: vcvt.f32.u32
+ %2 = uitofp <4 x i16> %1 to <4 x float>
+ %3 = extractelement <4 x float> %2, i32 0
+ %4 = extractelement <4 x float> %2, i32 1
+ %5 = extractelement <4 x float> %2, i32 2
+
+ ; CHECK: vadd.f32
+ %6 = fadd float %3, %4
+ %7 = fadd float %6, %5
+
+ ret float %7
+}
+
+; CHECK: g:
+define float @g(<4 x i8>* nocapture %in) {
+ ; CHECK: vldr
+ ; CHECK: vmovl.u8
+ ; CHECK: vmovl.u16
+ %1 = load <4 x i8>* %in
+ ; CHECK: vcvt.f32.u32
+ %2 = uitofp <4 x i8> %1 to <4 x float>
+ %3 = extractelement <4 x float> %2, i32 0
+ %4 = extractelement <4 x float> %2, i32 1
+ %5 = extractelement <4 x float> %2, i32 2
+
+ ; CHECK: vadd.f32
+ %6 = fadd float %3, %4
+ %7 = fadd float %6, %5
+
+ ret float %7
+}
+
+; CHECK: h:
+define <4 x i8> @h(<4 x float> %v) {
+ ; CHECK: vcvt.{{[us]}}32.f32
+ ; CHECK: vmovn.i32
+ %1 = fptoui <4 x float> %v to <4 x i8>
+ ret <4 x i8> %1
+}