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| author | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
| commit | 5bafff36c798608a189c517d37527e4a38863071 (patch) | |
| tree | 79bd2abbc5253e6f00db07023cf7d829cbcdee5a /test/CodeGen/ARM/vshrn.ll | |
| parent | 5de83afcdc3f4f0edf8caacba523f5d05ee48048 (diff) | |
| download | llvm-5bafff36c798608a189c517d37527e4a38863071.tar.gz llvm-5bafff36c798608a189c517d37527e4a38863071.tar.bz2 llvm-5bafff36c798608a189c517d37527e4a38863071.tar.xz | |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vshrn.ll')
| -rw-r--r-- | test/CodeGen/ARM/vshrn.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll new file mode 100644 index 0000000000..bc640cbbca --- /dev/null +++ b/test/CodeGen/ARM/vshrn.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vshrn\\.i16} %t | count 1 +; RUN: grep {vshrn\\.i32} %t | count 1 +; RUN: grep {vshrn\\.i64} %t | count 1 + +define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone |