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author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/CodeGen/ARM64/fast-isel-fcmp.ll | |
parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64/fast-isel-fcmp.ll')
-rw-r--r-- | test/CodeGen/ARM64/fast-isel-fcmp.ll | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/fast-isel-fcmp.ll b/test/CodeGen/ARM64/fast-isel-fcmp.ll new file mode 100644 index 0000000000..cf71fab714 --- /dev/null +++ b/test/CodeGen/ARM64/fast-isel-fcmp.ll @@ -0,0 +1,146 @@ +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s + +define zeroext i1 @fcmp_float1(float %a) nounwind ssp { +entry: +; CHECK: @fcmp_float1 +; CHECK: fcmp s0, #0.0 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq + %cmp = fcmp une float %a, 0.000000e+00 + ret i1 %cmp +} + +define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp { +entry: +; CHECK: @fcmp_float2 +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq + %cmp = fcmp une float %a, %b + ret i1 %cmp +} + +define zeroext i1 @fcmp_double1(double %a) nounwind ssp { +entry: +; CHECK: @fcmp_double1 +; CHECK: fcmp d0, #0.0 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq + %cmp = fcmp une double %a, 0.000000e+00 + ret i1 %cmp +} + +define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp { +entry: +; CHECK: @fcmp_double2 +; CHECK: fcmp d0, d1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq + %cmp = fcmp une double %a, %b + ret i1 %cmp +} + +; Check each fcmp condition +define float @fcmp_oeq(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_oeq +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne + %cmp = fcmp oeq float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ogt(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ogt +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le + %cmp = fcmp ogt float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_oge(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_oge +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt + %cmp = fcmp oge float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_olt(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_olt +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl + %cmp = fcmp olt float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ole(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ole +; CHECK: fcmp s0, s1 +; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi + %cmp = fcmp ole float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ord(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ord +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vs + %cmp = fcmp ord float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_uno(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_uno +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vc + %cmp = fcmp uno float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ugt(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ugt +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ls + %cmp = fcmp ugt float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_uge(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_uge +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, mi + %cmp = fcmp uge float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ult(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ult +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ge + %cmp = fcmp ult float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_ule(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_ule +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, gt + %cmp = fcmp ule float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} + +define float @fcmp_une(float %a, float %b) nounwind ssp { +; CHECK: @fcmp_une +; CHECK: fcmp s0, s1 +; CHECK: csinc {{w[0-9]+}}, wzr, wzr, eq + %cmp = fcmp une float %a, %b + %conv = uitofp i1 %cmp to float + ret float %conv +} |