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| author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
| commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
| tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/CodeGen/ARM64/long-shift.ll | |
| parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
| download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz | |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64/long-shift.ll')
| -rw-r--r-- | test/CodeGen/ARM64/long-shift.ll | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/long-shift.ll b/test/CodeGen/ARM64/long-shift.ll new file mode 100644 index 0000000000..6f37044d1a --- /dev/null +++ b/test/CodeGen/ARM64/long-shift.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s + +define i128 @shl(i128 %r, i128 %s) nounwind readnone { +; CHECK-LABEL: shl: +; CHECK: lslv [[XREG_0:x[0-9]+]], x1, x2 +; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40 +; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2 +; CHECK-NEXT: lsrv [[XREG_3:x[0-9]+]], x0, [[XREG_2]] +; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]] +; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64 +; CHECK-NEXT: lslv [[XREG_5:x[0-9]+]], x0, [[XREG_4]] +; CHECK-NEXT: cmp [[XREG_4]], #0 +; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge +; CHECK-NEXT: lslv [[SMALLSHIFT_LO:x[0-9]+]], x0, x2 +; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge +; CHECK-NEXT: ret + + %shl = shl i128 %r, %s + ret i128 %shl +} + +define i128 @ashr(i128 %r, i128 %s) nounwind readnone { +; CHECK: ashr: +; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2 +; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40 +; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2 +; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]] +; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]] +; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64 +; CHECK-NEXT: asrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]] +; CHECK-NEXT: cmp [[XREG_5]], #0 +; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge +; CHECK-NEXT: asrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2 +; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63 +; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge +; CHECK-NEXT: ret + + %shr = ashr i128 %r, %s + ret i128 %shr +} + +define i128 @lshr(i128 %r, i128 %s) nounwind readnone { +; CHECK: lshr: +; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2 +; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40 +; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2 +; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]] +; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]] +; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64 +; CHECK-NEXT: lsrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]] +; CHECK-NEXT: cmp [[XREG_5]], #0 +; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge +; CHECK-NEXT: lsrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2 +; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge +; CHECK-NEXT: ret + + %shr = lshr i128 %r, %s + ret i128 %shr +} |