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author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/CodeGen/ARM64/vcnt.ll | |
parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64/vcnt.ll')
-rw-r--r-- | test/CodeGen/ARM64/vcnt.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/vcnt.ll b/test/CodeGen/ARM64/vcnt.ll new file mode 100644 index 0000000000..e00658a4bd --- /dev/null +++ b/test/CodeGen/ARM64/vcnt.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s + +define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind { +;CHECK-LABEL: cls_8b: +;CHECK: cls.8b + %tmp1 = load <8 x i8>* %A + %tmp3 = call <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp3 +} + +define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind { +;CHECK-LABEL: cls_16b: +;CHECK: cls.16b + %tmp1 = load <16 x i8>* %A + %tmp3 = call <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp3 +} + +define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind { +;CHECK-LABEL: cls_4h: +;CHECK: cls.4h + %tmp1 = load <4 x i16>* %A + %tmp3 = call <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp3 +} + +define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind { +;CHECK-LABEL: cls_8h: +;CHECK: cls.8h + %tmp1 = load <8 x i16>* %A + %tmp3 = call <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp3 +} + +define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind { +;CHECK-LABEL: cls_2s: +;CHECK: cls.2s + %tmp1 = load <2 x i32>* %A + %tmp3 = call <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp3 +} + +define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind { +;CHECK-LABEL: cls_4s: +;CHECK: cls.4s + %tmp1 = load <4 x i32>* %A + %tmp3 = call <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8>) nounwind readnone +declare <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16>) nounwind readnone +declare <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32>) nounwind readnone +declare <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32>) nounwind readnone |