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author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/CodeGen/ARM64/zextload-unscaled.ll | |
parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64/zextload-unscaled.ll')
-rw-r--r-- | test/CodeGen/ARM64/zextload-unscaled.ll | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/zextload-unscaled.ll b/test/CodeGen/ARM64/zextload-unscaled.ll new file mode 100644 index 0000000000..c475dbd21e --- /dev/null +++ b/test/CodeGen/ARM64/zextload-unscaled.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=arm64 < %s | FileCheck %s + +@var32 = global i32 0 + +define void @test_zextloadi1_unscaled(i1* %base) { +; CHECK-LABEL: test_zextloadi1_unscaled: +; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7] + + %addr = getelementptr i1* %base, i32 -7 + %val = load i1* %addr, align 1 + + %extended = zext i1 %val to i32 + store i32 %extended, i32* @var32, align 4 + ret void +} + +define void @test_zextloadi8_unscaled(i8* %base) { +; CHECK-LABEL: test_zextloadi8_unscaled: +; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7] + + %addr = getelementptr i8* %base, i32 -7 + %val = load i8* %addr, align 1 + + %extended = zext i8 %val to i32 + store i32 %extended, i32* @var32, align 4 + ret void +} + +define void @test_zextloadi16_unscaled(i16* %base) { +; CHECK-LABEL: test_zextloadi16_unscaled: +; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14] + + %addr = getelementptr i16* %base, i32 -7 + %val = load i16* %addr, align 2 + + %extended = zext i16 %val to i32 + store i32 %extended, i32* @var32, align 4 + ret void +} + |