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author | Evan Cheng <evan.cheng@apple.com> | 2011-09-20 21:38:18 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-09-20 21:38:18 +0000 |
commit | 0d18174f0f138e98fcb8348b735a90add45428b8 (patch) | |
tree | b7144003b01c53b3ee91bab049945a3e5a88f337 /test/CodeGen/ARM | |
parent | 1daa5bea5858ca9d05ab6da1a38a66471e26a7a6 (diff) | |
download | llvm-0d18174f0f138e98fcb8348b735a90add45428b8.tar.gz llvm-0d18174f0f138e98fcb8348b735a90add45428b8.tar.bz2 llvm-0d18174f0f138e98fcb8348b735a90add45428b8.tar.xz |
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r-- | test/CodeGen/ARM/mulhi.ll | 44 |
1 files changed, 38 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll index 148f291e55..932004c5dd 100644 --- a/test/CodeGen/ARM/mulhi.ll +++ b/test/CodeGen/ARM/mulhi.ll @@ -1,9 +1,16 @@ -; RUN: llc < %s -march=arm -mattr=+v6 -; RUN: llc < %s -march=arm -mattr=+v6 | \ -; RUN: grep smmul | count 1 -; RUN: llc < %s -march=arm | grep umull | count 1 +; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6 +; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4 +; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3 -define i32 @smulhi(i32 %x, i32 %y) { +define i32 @smulhi(i32 %x, i32 %y) nounwind { +; V6: smulhi: +; V6: smmul + +; V4: smulhi: +; V4: smull + +; M3: smulhi: +; M3: smull %tmp = sext i32 %x to i64 ; <i64> [#uses=1] %tmp1 = sext i32 %y to i64 ; <i64> [#uses=1] %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1] @@ -12,7 +19,15 @@ define i32 @smulhi(i32 %x, i32 %y) { ret i32 %tmp3.upgrd.1 } -define i32 @umulhi(i32 %x, i32 %y) { +define i32 @umulhi(i32 %x, i32 %y) nounwind { +; V6: umulhi: +; V6: umull + +; V4: umulhi: +; V4: umull + +; M3: umulhi: +; M3: umull %tmp = zext i32 %x to i64 ; <i64> [#uses=1] %tmp1 = zext i32 %y to i64 ; <i64> [#uses=1] %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1] @@ -20,3 +35,20 @@ define i32 @umulhi(i32 %x, i32 %y) { %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1] ret i32 %tmp3.upgrd.2 } + +; rdar://r10152911 +define i32 @t3(i32 %a) nounwind { +; V6: t3: +; V6: smmla + +; V4: t3: +; V4: smull + +; M3: t3: +; M3-NOT: smmla +; M3: smull +entry: + %tmp1 = mul nsw i32 %a, 3 + %tmp2 = sdiv i32 %tmp1, 23 + ret i32 %tmp2 +} |