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| author | Louis Gerbarg <lgg@apple.com> | 2014-05-09 17:02:49 +0000 |
|---|---|---|
| committer | Louis Gerbarg <lgg@apple.com> | 2014-05-09 17:02:49 +0000 |
| commit | 7a9fbab1823e915aa7e2eb7536652d2a3ef8a38a (patch) | |
| tree | d19df1fa9b9fac637b912039595bea4c9133827d /test/CodeGen/ARM | |
| parent | c0adfbb49d674dc04f39536151f05cc6a5e9e5fb (diff) | |
| download | llvm-7a9fbab1823e915aa7e2eb7536652d2a3ef8a38a.tar.gz llvm-7a9fbab1823e915aa7e2eb7536652d2a3ef8a38a.tar.bz2 llvm-7a9fbab1823e915aa7e2eb7536652d2a3ef8a38a.tar.xz | |
Add custom lowering for add/sub with overflow intrinsics to ARM
This patch adds support to ARM for custom lowering of the
llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful
for handling idiomatic saturating math functions as generated by
InstCombineCompare.
Test cases included.
rdar://14853450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208435 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/intrinsics-overflow.ll | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/intrinsics-overflow.ll b/test/CodeGen/ARM/intrinsics-overflow.ll new file mode 100644 index 0000000000..c414add59f --- /dev/null +++ b/test/CodeGen/ARM/intrinsics-overflow.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -march=arm -mcpu=generic | FileCheck %s + +define i32 @uadd_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: uadd_overflow: + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movhs r[[R1]], #0 +} + + +define i32 @sadd_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: sadd_overflow: + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movvc r[[R1]], #0 +} + +define i32 @usub_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: usub_overflow: + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movhs r[[R2]], #0 +} + +define i32 @ssub_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: ssub_overflow: + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movvc r[[R2]], #0 +} + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 +declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2 +declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3 +declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4 |