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authorBob Wilson <bob.wilson@apple.com>2011-08-13 05:14:55 +0000
committerBob Wilson <bob.wilson@apple.com>2011-08-13 05:14:55 +0000
commit7dcd04abe0b0b1dbfb285faea2daece50f9aa502 (patch)
treeebca6f2095da1dc75aea8adeabef7be3b794ce31 /test/CodeGen/ARM
parent53b2b7364385b2f2d98c0052df73a637a81c2288 (diff)
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Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll13
1 files changed, 13 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
new file mode 100644
index 0000000000..6afa0161ca
--- /dev/null
+++ b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
@@ -0,0 +1,13 @@
+; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0
+; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
+; Make sure that it gets expanded; otherwise, the compile fails when trying
+; to print the pseudo-instruction.
+
+define void @test_vmovqqqq_pseudo() nounwind ssp {
+entry:
+ %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
+ store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
+ ret void
+}
+
+declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly