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authorEvan Cheng <evan.cheng@apple.com>2011-09-28 23:16:31 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-09-28 23:16:31 +0000
commit9b88d2d7827d19ef05d3f11faf56e4f28aaa7072 (patch)
tree7b9a06de22730ef1853cfea61e85254e48c99129 /test/CodeGen/ARM
parentd42ca4607b840b65141b42788b5fef6c08e22aa6 (diff)
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Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll30
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
new file mode 100644
index 0000000000..c6f4a93def
--- /dev/null
+++ b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s
+
+; rdar://10196296
+; ARM target specific dag combine created a cycle in DAG.
+
+define void @t() nounwind ssp {
+ %1 = load i64* undef, align 4
+ %2 = shl i32 5, 0
+ %3 = zext i32 %2 to i64
+ %4 = and i64 %1, %3
+ %5 = lshr i64 %4, undef
+ switch i64 %5, label %8 [
+ i64 0, label %9
+ i64 1, label %6
+ i64 4, label %9
+ i64 5, label %7
+ ]
+
+; <label>:6 ; preds = %0
+ unreachable
+
+; <label>:7 ; preds = %0
+ unreachable
+
+; <label>:8 ; preds = %0
+ unreachable
+
+; <label>:9 ; preds = %0, %0
+ ret void
+}