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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-08-31 18:26:09 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-08-31 18:26:09 +0000 |
| commit | ba567d670d32e102a70b106fbfe284835085cb3f (patch) | |
| tree | 866740f90153a4f06cc20acbfbe82078c1e7d625 /test/CodeGen/ARM | |
| parent | 72335d55d972dd7279fe68ed05fa3c4e7fce9345 (diff) | |
| download | llvm-ba567d670d32e102a70b106fbfe284835085cb3f.tar.gz llvm-ba567d670d32e102a70b106fbfe284835085cb3f.tar.bz2 llvm-ba567d670d32e102a70b106fbfe284835085cb3f.tar.xz | |
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/atomic-64bit.ll | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index abe1acc6d1..e9609ac0f9 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -6,7 +6,7 @@ define i64 @test1(i64* %ptr, i64 %val) { ; CHECK: ldrexd r2, r3 ; CHECK: adds r0, r2 ; CHECK: adc r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -20,7 +20,7 @@ define i64 @test2(i64* %ptr, i64 %val) { ; CHECK: ldrexd r2, r3 ; CHECK: subs r0, r2 ; CHECK: sbc r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -34,7 +34,7 @@ define i64 @test3(i64* %ptr, i64 %val) { ; CHECK: ldrexd r2, r3 ; CHECK: and r0, r2 ; CHECK: and r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -48,7 +48,7 @@ define i64 @test4(i64* %ptr, i64 %val) { ; CHECK: ldrexd r2, r3 ; CHECK: orr r0, r2 ; CHECK: orr r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -62,7 +62,7 @@ define i64 @test5(i64* %ptr, i64 %val) { ; CHECK: ldrexd r2, r3 ; CHECK: eor r0, r2 ; CHECK: eor r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -74,7 +74,7 @@ define i64 @test6(i64* %ptr, i64 %val) { ; CHECK: test6 ; CHECK: dmb ish ; CHECK: ldrexd r2, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -89,10 +89,40 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { ; CHECK: cmp r2 ; CHECK: cmpeq r3 ; CHECK: bne -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst ret i64 %r } + +; Compiles down to cmpxchg +; FIXME: Should compile to a single ldrexd +define i64 @test8(i64* %ptr) { +; CHECK: test8 +; CHECK: ldrexd r2, r3 +; CHECK: cmp r2 +; CHECK: cmpeq r3 +; CHECK: bne +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = load atomic i64* %ptr seq_cst, align 8 + ret i64 %r +} + +; Compiles down to atomicrmw xchg; there really isn't any more efficient +; way to write it. +define void @test9(i64* %ptr, i64 %val) { +; CHECK: test9 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + store atomic i64 %val, i64* %ptr seq_cst, align 8 + ret void +} |