diff options
| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-05 18:42:28 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-05 18:42:28 +0000 |
| commit | ee0ef13eba037055d8dc315fc924d967c8f8ce0a (patch) | |
| tree | 886e7aa9b4bc9ddf16917fda1fa75d1b9c5b3b42 /test/CodeGen/Hexagon | |
| parent | 62f38ca141f87ff3ed9334fbe6a5e1c45d40ca86 (diff) | |
| download | llvm-ee0ef13eba037055d8dc315fc924d967c8f8ce0a.tar.gz llvm-ee0ef13eba037055d8dc315fc924d967c8f8ce0a.tar.bz2 llvm-ee0ef13eba037055d8dc315fc924d967c8f8ce0a.tar.xz | |
Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/args.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/dualstore.ll | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/Hexagon/args.ll b/test/CodeGen/Hexagon/args.ll index 767a442612..f8c9e44c83 100644 --- a/test/CodeGen/Hexagon/args.ll +++ b/test/CodeGen/Hexagon/args.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s ; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7 -; CHECK: r5 = #6 ; CHECK: r0 = #1 ; CHECK: r1 = #2 ; CHECK: r2 = #3 ; CHECK: r3 = #4 ; CHECK: r4 = #5 +; CHECK: r5 = #6 define void @foo() nounwind { diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll index 3bf60193a2..f7d7e8bbe7 100644 --- a/test/CodeGen/Hexagon/dualstore.ll +++ b/test/CodeGen/Hexagon/dualstore.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s ; Check that we generate dual stores in one packet in V4 -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000 -; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000 +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000 +; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000 ; CHECK-NEXT: } @Reg = global i32 0, align 4 |