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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-14 00:21:25 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-14 00:21:25 +0000 |
| commit | bfb07b1054b653661306848e695b34e79289a15b (patch) | |
| tree | 6fd12b1ef61dad5b51560f52ddbba36ae9910d5f /test/CodeGen/Mips/2008-08-01-AsmInline.ll | |
| parent | eaa8f5533f9f678fe3c56aec0201a34e46eaaf54 (diff) | |
| download | llvm-bfb07b1054b653661306848e695b34e79289a15b.tar.gz llvm-bfb07b1054b653661306848e695b34e79289a15b.tar.bz2 llvm-bfb07b1054b653661306848e695b34e79289a15b.tar.xz | |
[mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/2008-08-01-AsmInline.ll')
| -rw-r--r-- | test/CodeGen/Mips/2008-08-01-AsmInline.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/test/CodeGen/Mips/2008-08-01-AsmInline.ll index dbde742ad3..e274bc0e14 100644 --- a/test/CodeGen/Mips/2008-08-01-AsmInline.ll +++ b/test/CodeGen/Mips/2008-08-01-AsmInline.ll @@ -51,3 +51,21 @@ entry: ret void } +; Check that RA doesn't allocate registers in the clobber list. +; CHECK-LABEL: foo4: +; CHECK: #APP +; CHECK-NOT: ulh $2 +; CHECK: #NO_APP +; CHECK: #APP +; CHECK-NOT: $f0 +; CHECK: #NO_APP + +define void @foo4() { +entry: + %0 = tail call i32 asm sideeffect "ulh $0,16($$sp)\0A\09", "=r,~{$2}"() + store i32 %0, i32* @gi2, align 4 + %1 = load float* @gf0, align 4 + %2 = tail call double asm sideeffect "cvt.d.s $0, $1\0A\09", "=f,f,~{$f0}"(float %1) + store double %2, double* @gd0, align 8 + ret void +} |