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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
| commit | f1ef27e6e308435035ffec112a6474ed5e009484 (patch) | |
| tree | e95a12e18af12ddcc5e485c2bce80ccbd3decd89 /test/CodeGen/Mips/msa/3r_splat.ll | |
| parent | d2a31a124f3bebbdfc4d886afe33a116893aa689 (diff) | |
| download | llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.gz llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.bz2 llvm-f1ef27e6e308435035ffec112a6474ed5e009484.tar.xz | |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa/3r_splat.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/3r_splat.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll index 001f723f7d..2e604a43a0 100644 --- a/test/CodeGen/Mips/msa/3r_splat.ll +++ b/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,7 +1,7 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_splat_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 |