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| author | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
| commit | 87896d9368e08d93493427ce7bf8272d1e5cca35 (patch) | |
| tree | d3183747b2917bf4e1254c7a331ff86fd3352a2f /test/CodeGen/Mips/o32_cc_vararg.ll | |
| parent | f93f7b2446bec3febc30b7136e18704664bd98cc (diff) | |
| download | llvm-87896d9368e08d93493427ce7bf8272d1e5cca35.tar.gz llvm-87896d9368e08d93493427ce7bf8272d1e5cca35.tar.bz2 llvm-87896d9368e08d93493427ce7bf8272d1e5cca35.tar.xz | |
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/o32_cc_vararg.ll')
| -rw-r--r-- | test/CodeGen/Mips/o32_cc_vararg.ll | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index 6601d25055..1f71ed2640 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s ; All test functions do the same thing - they return the first variable ; argument. -; All CHECK's do the same thing - they check whether variable arguments from -; registers are placed on correct stack locations, and whether the first +; All CHECK's do the same thing - they check whether variable arguments from +; registers are placed on correct stack locations, and whether the first ; variable argument is returned from the correct stack location. @@ -31,14 +31,14 @@ entry: ; CHECK: va1: ; CHECK: addiu $sp, $sp, -32 -; CHECK: sw $5, 36($sp) -; CHECK: sw $6, 40($sp) ; CHECK: sw $7, 44($sp) +; CHECK: sw $6, 40($sp) +; CHECK: sw $5, 36($sp) ; CHECK: lw $2, 36($sp) } -; check whether the variable double argument will be accessed from the 8-byte -; aligned location (i.e. whether the address is computed by adding 7 and +; check whether the variable double argument will be accessed from the 8-byte +; aligned location (i.e. whether the address is computed by adding 7 and ; clearing lower 3 bits) define double @va2(i32 %a, ...) nounwind { entry: @@ -57,10 +57,10 @@ entry: ; CHECK: va2: ; CHECK: addiu $sp, $sp, -40 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 44 -; CHECK: sw $5, 44($sp) -; CHECK: sw $6, 48($sp) ; CHECK: sw $7, 52($sp) +; CHECK: sw $6, 48($sp) +; CHECK: sw $5, 44($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 44 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] @@ -85,8 +85,8 @@ entry: ; CHECK: va3: ; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $6, 48($sp) ; CHECK: sw $7, 52($sp) +; CHECK: sw $6, 48($sp) ; CHECK: lw $2, 48($sp) } @@ -108,8 +108,8 @@ entry: ; CHECK: va4: ; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $6, 56($sp) ; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) ; CHECK: addiu $[[R0:[0-9]+]], $sp, 56 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 |