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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-02 23:07:05 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-02 23:07:05 +0000 |
commit | 99ad6ac65e8c97a0d3c9d884285dda01f793b7d1 (patch) | |
tree | a8d0b570daa7b8d415766c5425bd39b8217f5f25 /test/CodeGen/Mips | |
parent | 53f1b19c6e0b0b2fe2dfccd543738a20241c8e78 (diff) | |
download | llvm-99ad6ac65e8c97a0d3c9d884285dda01f793b7d1.tar.gz llvm-99ad6ac65e8c97a0d3c9d884285dda01f793b7d1.tar.bz2 llvm-99ad6ac65e8c97a0d3c9d884285dda01f793b7d1.tar.xz |
[mips] Handle reading, writing or copying of ccond field of DSP control
register.
- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
-rw-r--r-- | test/CodeGen/Mips/spill-copy-acreg.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/spill-copy-acreg.ll b/test/CodeGen/Mips/spill-copy-acreg.ll index 2ca031a104..6563a5cffd 100644 --- a/test/CodeGen/Mips/spill-copy-acreg.ll +++ b/test/CodeGen/Mips/spill-copy-acreg.ll @@ -19,3 +19,23 @@ entry: declare i64 @llvm.mips.maddu(i64, i32, i32) declare void @foo1() + +@g4 = common global <2 x i16> zeroinitializer, align 4 +@g5 = common global <2 x i16> zeroinitializer, align 4 +@g6 = common global <2 x i16> zeroinitializer, align 4 + +define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %cmp3 = icmp slt <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp3 to <2 x i16> + store <2 x i16> %sext, <2 x i16>* @g4, align 4 + tail call void @foo1() + %2 = load <2 x i16>* @g5, align 4 + %3 = load <2 x i16>* @g6, align 4 + %or = select <2 x i1> %cmp3, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} |