Use multiple virtual registers in PPC CR spilling

Now that the register scavenger can support multiple spill slots, and PEI can
use virtual-register-based scavenging for multiple simultaneous registers, we
can use a virtual register for the transfer register in the CR spilling code.

This should eliminate the last place (outside of the prologue/epilogue) where
we depend on the unconditional availability of the r0 register. We will soon be
able to allocate it (in a somewhat restricted sense) as a GPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 17 deletions

diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 0da6e4351b..79e8f96b39 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -2,21 +2,22 @@
 ; ModuleID = 'hh.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 target triple = "powerpc-apple-darwin9.6"
-; This formerly used R0 for both the stack address and CR.
 
 define void @foo() nounwind {
 entry:
-;CHECK:  mfcr r0
-;CHECK:  lis r2, 1
-;CHECK:  rlwinm r0, r0, 8, 0, 31
-;CHECK:  ori r2, r2, 34540
-;CHECK:  stwx r0, r1, r2
-; Make sure that the register scavenger returns the same temporary register.
-;CHECK:  lis r2, 1
-;CHECK:  mfcr r0
-;CHECK:  ori r2, r2, 34536
-;CHECK:  rlwinm r0, r0, 12, 0, 31
-;CHECK:  stwx r0, r1, r2
+; Note that part of what is being checked here is proper register reuse.
+; CHECK: mfcr [[T1:r[0-9]+]]                         ; cr2
+; CHECK: lis [[T2:r[0-9]+]], 1
+; FIXME: There should only be one lis needed here!
+; CHECK: lis [[T3:r[0-9]+]], 1
+; CHECK: addi r3, r1, 72
+; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31
+; CHECK: ori [[T2]], [[T2]], 34540
+; CHECK: ori [[T3]], [[T3]], 34536
+; CHECK: stwx [[T1]], r1, [[T2]]
+; CHECK: mfcr [[T4:r[0-9]+]]                         ; cr3
+; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31
+; CHECK: stwx r4, r1, [[T3]]
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
@@ -25,11 +26,16 @@ entry:
   br label %return
 
 return:                                           ; preds = %entry
-;CHECK:  lis r2, 1
-;CHECK:  ori r2, r2, 34540
-;CHECK:  lwzx r0, r1, r2
-;CHECK:  rlwinm r0, r0, 24, 0, 31
-;CHECK:  mtcrf 32, r0
+; CHECK: lis [[T1:r[0-9]+]], 1
+; CHECK: ori [[T1]], [[T1]], 34536
+; CHECK: lwzx [[T1]], r1, [[T1]]
+; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31
+; CHECK: mtcrf 16, [[T1]]
+; CHECK: lis [[T1]], 1
+; CHECK: ori [[T1]], [[T1]], 34540
+; CHECK: lwzx [[T1]], r1, [[T1]]
+; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31
+; CHECK: mtcrf 32, [[T1]]
   ret void
 }