diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 17:43:32 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 17:43:32 +0000 |
| commit | e2ff00e117ba9b758b298e671f65c0b002f8a52d (patch) | |
| tree | 0ff554f2b4d87dd050c175dbfa8a95fdf0f5ba2e /test/CodeGen/PowerPC/set0-v8i16.ll | |
| parent | 53b28f86236fc548143656929f39f38d9dc83e06 (diff) | |
| download | llvm-e2ff00e117ba9b758b298e671f65c0b002f8a52d.tar.gz llvm-e2ff00e117ba9b758b298e671f65c0b002f8a52d.tar.bz2 llvm-e2ff00e117ba9b758b298e671f65c0b002f8a52d.tar.xz | |
PPC: Add some missing V_SET0 patterns
We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for
v8i16 (which occurs in the test case) or v16i8. The same was true for
V_SETALLONES (so I added the associated patterns for those as well).
Another bug found by llvm-stress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186108 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/set0-v8i16.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/set0-v8i16.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/set0-v8i16.ll b/test/CodeGen/PowerPC/set0-v8i16.ll new file mode 100644 index 0000000000..13d51dfc8e --- /dev/null +++ b/test/CodeGen/PowerPC/set0-v8i16.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD367951() { +BB: + %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24> + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18> + %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer + %E27 = extractelement <16 x i1> %Cmp11, i32 5 + br label %CF76 + +CF76: ; preds = %CF80, %CF76, %BB + br i1 undef, label %CF76, label %CF80 + +CF80: ; preds = %CF76 + %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff + br label %CF76 +} |