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| author | Hal Finkel <hfinkel@anl.gov> | 2013-08-14 20:05:04 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-08-14 20:05:04 +0000 |
| commit | 341c1a50adeadd848b2e73e9184d81331ee1cb92 (patch) | |
| tree | 7ef87c37606aa4bd9da6beb46b20c9da9bc421f9 /test/CodeGen/PowerPC | |
| parent | fdb1a6c341c0e289f3f900cdab87f831262c0e93 (diff) | |
| download | llvm-341c1a50adeadd848b2e73e9184d81331ee1cb92.tar.gz llvm-341c1a50adeadd848b2e73e9184d81331ee1cb92.tar.bz2 llvm-341c1a50adeadd848b2e73e9184d81331ee1cb92.tar.xz | |
Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/inlineasm-i64-reg.ll | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll index fa9aa45b94..5e31cd5830 100644 --- a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll +++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll @@ -59,6 +59,49 @@ entry: ret i32 %conv } +declare void @mtrace() + +define signext i32 @main(i32 signext %argc, i8** %argv) { +entry: + %argc.addr = alloca i32, align 4 + store i32 %argc, i32* %argc.addr, align 4 + %0 = call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1076) + %asmresult1.i = extractvalue { i64, i64 } %0, 1 + %conv.i = trunc i64 %asmresult1.i to i32 + %cmp = icmp eq i32 %conv.i, 0 + br i1 %cmp, label %if.then, label %if.end + +; CHECK-LABEL: @main + +; CHECK-DAG: mr [[REG:[0-9]+]], 3 +; CHECK-DAG: li 0, 1076 +; CHECK: stw [[REG]], + +; CHECK: #APP +; CHECK: sc +; CHECK: #NO_APP + +; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1 + +; CHECK: blr + +if.then: ; preds = %entry + call void @mtrace() + %.pre = load i32* %argc.addr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + %1 = phi i32 [ %.pre, %if.then ], [ %argc, %entry ] + %cmp1 = icmp slt i32 %1, 2 + br i1 %cmp1, label %usage, label %if.end40 + +usage: + ret i32 8 + +if.end40: + ret i32 0 +} + attributes #0 = { alwaysinline inlinehint nounwind } attributes #1 = { nounwind } |