diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-15 02:07:05 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-15 02:07:05 +0000 |
| commit | fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36 (patch) | |
| tree | 1eaf007fd39fc7cc978f37018068a9428ea3daf2 /test/CodeGen/PowerPC | |
| parent | f1216abf7ec0d37152a0aaaad5a238beca65ecb6 (diff) | |
| download | llvm-fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36.tar.gz llvm-fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36.tar.bz2 llvm-fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36.tar.xz | |
Fix PPC64 CR spill location for callee-saved registers
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).
So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.
In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/crsave.ll | 29 |
1 files changed, 10 insertions, 19 deletions
diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index 109e595900..d698ab031d 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 -; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64-FP ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 declare void @foo() @@ -20,14 +19,11 @@ entry: ; PPC32-NEXT: mtcrf 32, 12 ; PPC64: mfcr 12 -; PPC64-NEXT: stw 12, 8(1) +; PPC64: stw 12, 8(1) +; PPC64: stdu 1, -[[AMT:[0-9]+]](1) +; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64-NEXT: mtcrf 32, 12 - -; PPC64-FP: mfcr 12 -; PPC64-FP-NEXT: stw 12, 8(31) -; PPC64-FP: lwz 12, 8(31) -; PPC64-FP-NEXT: mtcrf 32, 12 +; PPC64: mtcrf 32, 12 define i32 @test_cr234() nounwind { entry: @@ -47,16 +43,11 @@ entry: ; PPC32-NEXT: mtcrf 8, 12 ; PPC64: mfcr 12 -; PPC64-NEXT: stw 12, 8(1) +; PPC64: stw 12, 8(1) +; PPC64: stdu 1, -[[AMT:[0-9]+]](1) +; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64-NEXT: mtcrf 32, 12 -; PPC64-NEXT: mtcrf 16, 12 -; PPC64-NEXT: mtcrf 8, 12 - -; PPC64-FP: mfcr 12 -; PPC64-FP-NEXT: stw 12, 8(31) -; PPC64-FP: lwz 12, 8(31) -; PPC64-FP-NEXT: mtcrf 32, 12 -; PPC64-FP-NEXT: mtcrf 16, 12 -; PPC64-FP-NEXT: mtcrf 8, 12 +; PPC64: mtcrf 32, 12 +; PPC64: mtcrf 16, 12 +; PPC64: mtcrf 8, 12 |