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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 692ee102ebef535d311c35d53457028083e5c5be (patch) | |
| tree | 5966632bb87e4120a27dadfce4187535429a4275 /test/CodeGen/R600/fmul.ll | |
| parent | 98b357e1cd0d41108e6011725dad6a6dbf208a38 (diff) | |
| download | llvm-692ee102ebef535d311c35d53457028083e5c5be.tar.gz llvm-692ee102ebef535d311c35d53457028083e5c5be.tar.bz2 llvm-692ee102ebef535d311c35d53457028083e5c5be.tar.xz | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fmul.ll')
| -rw-r--r-- | test/CodeGen/R600/fmul.ll | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index a40e818c12..6ef3a11767 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -15,6 +15,16 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fmul_v2f32 +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}} +define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fmul <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + ; CHECK: @fmul_v4f32 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |