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| author | Vincent Lejeune <vljn@ovi.com> | 2013-07-31 19:31:56 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-07-31 19:31:56 +0000 |
| commit | 98ce62780ea7185ba710868bf83c8077e8d7f6d6 (patch) | |
| tree | 639ca4cbedb749ce5b4969fa112df1dbe35f6cd9 /test/CodeGen/R600/fmul.ll | |
| parent | a92f8ee2f3ee12d26f6ed0720c763021cfa22ca8 (diff) | |
| download | llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.tar.gz llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.tar.bz2 llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.tar.xz | |
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fmul.ll')
| -rw-r--r-- | test/CodeGen/R600/fmul.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index a40e818c12..eec673c958 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; CHECK: @fmul_v4f32 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { |