R600/SI: Add support for 64-bit loads

https://bugs.freedesktop.org/show_bug.cgi?id=65873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186339 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 42 insertions, 0 deletions

diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index d1ebaa39f6..44c089ba69 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -65,3 +65,45 @@ define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(
   store float %1, float addrspace(1)* %out
   ret void
 }
+
+; R600-CHECK: @load_i64
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+
+; SI-CHECK: @load_i64
+; SI-CHECK: BUFFER_LOAD_DWORDX2
+define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
+entry:
+  %0 = load i64 addrspace(1)* %in
+  store i64 %0, i64 addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i64_sext
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}},  literal.x
+; R600-CHECK: 31
+; SI-CHECK: @load_i64_sext
+; SI-CHECK: BUFFER_LOAD_DWORDX2 [[VAL:VGPR[0-9]_VGPR[0-9]]]
+; SI-CHECK: V_LSHL_B64 [[LSHL:VGPR[0-9]_VGPR[0-9]]], [[VAL]], 32
+; SI-CHECK: V_ASHR_I64 VGPR{{[0-9]}}_VGPR{{[0-9]}}, [[LSHL]], 32
+
+define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+  %0 = load i32 addrspace(1)* %in
+  %1 = sext i32 %0 to i64
+  store i64 %1, i64 addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i64_zext
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+  %0 = load i32 addrspace(1)* %in
+  %1 = zext i32 %0 to i64
+  store i64 %1, i64 addrspace(1)* %out
+  ret void
+}