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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-24 20:08:13 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-24 20:08:13 +0000 |
| commit | add2e2ec8fcb21cc8a51387b2095fd1b4abc2f50 (patch) | |
| tree | 431987fb01a2f08b3695eac4c484e756bd78a6f3 /test/CodeGen/R600/or.ll | |
| parent | 3a96e61469fd80bbb2c5bcf2b4dcee89e3a68ab3 (diff) | |
| download | llvm-add2e2ec8fcb21cc8a51387b2095fd1b4abc2f50.tar.gz llvm-add2e2ec8fcb21cc8a51387b2095fd1b4abc2f50.tar.bz2 llvm-add2e2ec8fcb21cc8a51387b2095fd1b4abc2f50.tar.xz | |
R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/or.ll')
| -rw-r--r-- | test/CodeGen/R600/or.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index 8e985c75cb..be984b2712 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -89,11 +89,11 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, } ; SI-LABEL: @vector_or_i64_loadimm -; SI-DAG: S_MOV_B32 -; SI-DAG: S_MOV_B32 -; SI-DAG: BUFFER_LOAD_DWORDX2 -; SI: V_OR_B32_e32 -; SI: V_OR_B32_e32 +; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], -545810305 +; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 5231 +; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] +; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI: S_ENDPGM define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 |