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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-19 20:07:20 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-19 20:07:20 +0000 |
| commit | 21886a495a5467aa241f325cdd3dd2532fa7dcde (patch) | |
| tree | aeacb824b438f4a02414895b00bfd40189086bd6 /test/CodeGen/SPARC | |
| parent | 233a4d7124ecf9611804e3c75102cdcf7d2fd074 (diff) | |
| download | llvm-21886a495a5467aa241f325cdd3dd2532fa7dcde.tar.gz llvm-21886a495a5467aa241f325cdd3dd2532fa7dcde.tar.bz2 llvm-21886a495a5467aa241f325cdd3dd2532fa7dcde.tar.xz | |
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.
Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SPARC')
| -rw-r--r-- | test/CodeGen/SPARC/2011-01-19-DelaySlot.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll index a0878d3482..160062b3ec 100644 --- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll +++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll @@ -97,7 +97,7 @@ entry: ;CHECK-NEXT: nop %0 = add nsw i32 %i0, 2 %1 = add nsw i32 %i0, 3 - tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4}"(i32 %0, i32 %1) + tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o6},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1) %2 = add nsw i32 %0, %1 %3 = tail call i32 @bar(i32 %2) ret i32 %3 |