diff options
| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-09-02 18:32:45 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-09-02 18:32:45 +0000 |
| commit | 6ee0857bd74dd68e46e970a6bcf756ee03ed8e99 (patch) | |
| tree | 1352b253af92f7c73bef86ed467b6cf7aa497542 /test/CodeGen/SPARC | |
| parent | 195dd8a1ce38970e3463ee1425647280373b60a7 (diff) | |
| download | llvm-6ee0857bd74dd68e46e970a6bcf756ee03ed8e99.tar.gz llvm-6ee0857bd74dd68e46e970a6bcf756ee03ed8e99.tar.bz2 llvm-6ee0857bd74dd68e46e970a6bcf756ee03ed8e99.tar.xz | |
[Sparc] Implement spill and load for long double(f128) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189768 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SPARC')
| -rw-r--r-- | test/CodeGen/SPARC/fp128.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll index a3a8bfa489..1cc194b065 100644 --- a/test/CodeGen/SPARC/fp128.ll +++ b/test/CodeGen/SPARC/fp128.ll @@ -25,3 +25,18 @@ entry: store fp128 %7, fp128* %scalar.result, align 8 ret void } + +; CHECK-LABEL: f128_spill +; CHECK: std %f{{.+}}, [%[[S0:.+]]] +; CHECK: std %f{{.+}}, [%[[S1:.+]]] +; CHECK-DAG: ldd [%[[S0]]], %f{{.+}} +; CHECK-DAG: ldd [%[[S1]]], %f{{.+}} +; CHECK: jmp + +define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { +entry: + %0 = load fp128* %a, align 8 + call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() + store fp128 %0, fp128* %scalar.result, align 8 + ret void +} |