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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
| commit | b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9 (patch) | |
| tree | 67565add4984989a53566cb7836cfadc52f2e39e /test/CodeGen/SystemZ/atomicrmw-minmax-02.ll | |
| parent | 3ee0673e4f5f0324ecd0a65507009b0748ed072c (diff) | |
| download | llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.gz llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.bz2 llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.xz | |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/atomicrmw-minmax-02.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-minmax-02.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll index b2c7bc9028..78c95df11f 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll @@ -14,16 +14,16 @@ ; independent of the other loop prologue instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) ; CHECK: jlh [[LOOP]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 @@ -50,16 +50,16 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check signed maximum. define i16 @f2(i16 *%src, i16 %b) { ; CHECK: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) ; CHECK: jlh [[LOOP]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 @@ -86,9 +86,9 @@ define i16 @f2(i16 *%src, i16 %b) { ; Check unsigned minimum. define i16 @f3(i16 *%src, i16 %b) { ; CHECK: f3: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: clr [[ROT]], %r3 @@ -96,7 +96,7 @@ define i16 @f3(i16 *%src, i16 %b) { ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) ; CHECK: jlh [[LOOP]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 @@ -123,9 +123,9 @@ define i16 @f3(i16 *%src, i16 %b) { ; Check unsigned maximum. define i16 @f4(i16 *%src, i16 %b) { ; CHECK: f4: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]]) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: clr [[ROT]], %r3 @@ -133,7 +133,7 @@ define i16 @f4(i16 *%src, i16 %b) { ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]]) ; CHECK: jlh [[LOOP]] ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) ; CHECK: br %r14 |