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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-05-28 10:41:11 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-05-28 10:41:11 +0000 |
| commit | d50bcb2162a529534da42748ab4a418bfc9aaf06 (patch) | |
| tree | fc9a388bd749853d9a65985890f9a81f37391a8b /test/CodeGen/SystemZ/atomicrmw-minmax-02.ll | |
| parent | fe4716f7cf0bbabb5694fa452f435cec59bbd0e3 (diff) | |
| download | llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.gz llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.bz2 llvm-d50bcb2162a529534da42748ab4a418bfc9aaf06.tar.xz | |
[SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions. Support for
the immediate forms will be a separate patch.
The architecture has a large number of comparison instructions. I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction. The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/atomicrmw-minmax-02.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-minmax-02.ll | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll index 27dc3e925b..b2c7bc9028 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll @@ -19,8 +19,7 @@ define i16 @f1(i16 *%src, i16 %b) { ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) -; CHECK: cr [[ROT]], %r3 -; CHECK: jle [[KEEP:\..*]] +; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) @@ -40,7 +39,7 @@ define i16 @f1(i16 *%src, i16 %b) { ; CHECK-SHIFT2: f1: ; CHECK-SHIFT2: sll %r3, 16 ; CHECK-SHIFT2: rll -; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3 ; CHECK-SHIFT2: rll ; CHECK-SHIFT2: rll ; CHECK-SHIFT2: br %r14 @@ -56,8 +55,7 @@ define i16 @f2(i16 *%src, i16 %b) { ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) ; CHECK: [[LOOP:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) -; CHECK: cr [[ROT]], %r3 -; CHECK: jhe [[KEEP:\..*]] +; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) @@ -77,7 +75,7 @@ define i16 @f2(i16 *%src, i16 %b) { ; CHECK-SHIFT2: f2: ; CHECK-SHIFT2: sll %r3, 16 ; CHECK-SHIFT2: rll -; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3 ; CHECK-SHIFT2: rll ; CHECK-SHIFT2: rll ; CHECK-SHIFT2: br %r14 @@ -164,7 +162,7 @@ define i16 @f4(i16 *%src, i16 %b) { define i16 @f5(i16 *%src) { ; CHECK: f5: ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769 -; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]] ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 ; CHECK: br %r14 ; @@ -181,7 +179,7 @@ define i16 @f5(i16 *%src) { define i16 @f6(i16 *%src) { ; CHECK: f6: ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766 -; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]] ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 ; CHECK: br %r14 ; |