diff options
| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-28 13:53:37 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-28 13:53:37 +0000 |
| commit | 349baa60393c637f479ee31b25c65555b095a2ef (patch) | |
| tree | 80faee69092f3ce2360fd840c792a186dd74cfbc /test/CodeGen/SystemZ/int-add-10.ll | |
| parent | a7be36c8eb4717e44b05e00008544b883fc87de9 (diff) | |
| download | llvm-349baa60393c637f479ee31b25c65555b095a2ef.tar.gz llvm-349baa60393c637f479ee31b25c65555b095a2ef.tar.bz2 llvm-349baa60393c637f479ee31b25c65555b095a2ef.tar.xz | |
[SystemZ] Set usaAA to true
useAA significantly improves the handling of vector code that has TBAA
information attached. It also helps other cases, as shown by the testsuite
changes here. The only real downside I've seen is that it interferes with
MergeConsecutiveStores. The problem is that that optimization works top
down, starting at the first store in the chain, and looks for cases where
the chain result is only used by a single related store. These related
stores don't alias, so useAA will have rewritten all the later stores to
use a different chain input (typically the same one as the first store).
I think the advantages outweigh the disadvantages though, so for now I've
just disabled alias analysis for the unaligned-01.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193521 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/int-add-10.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/int-add-10.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll index 66a275bc6c..01d0a661ed 100644 --- a/test/CodeGen/SystemZ/int-add-10.ll +++ b/test/CodeGen/SystemZ/int-add-10.ll @@ -7,7 +7,7 @@ define void @f1(i128 *%aptr, i32 %b) { ; CHECK-LABEL: f1: ; CHECK: algfr {{%r[0-5]}}, %r3 -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -21,7 +21,7 @@ define void @f1(i128 *%aptr, i32 %b) { define void @f2(i128 *%aptr, i64 %b) { ; CHECK-LABEL: f2: ; CHECK: algfr {{%r[0-5]}}, %r3 -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -37,7 +37,7 @@ define void @f2(i128 *%aptr, i64 %b) { define void @f3(i128 *%aptr, i64 %b) { ; CHECK-LABEL: f3: ; CHECK: algfr {{%r[0-5]}}, %r3 -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -52,7 +52,7 @@ define void @f3(i128 *%aptr, i64 %b) { define void @f4(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f4: ; CHECK: algf {{%r[0-5]}}, 0(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -67,7 +67,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) { define void @f5(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f5: ; CHECK: algf {{%r[0-5]}}, 524284(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -85,7 +85,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f6: ; CHECK: agfi %r3, 524288 ; CHECK: algf {{%r[0-5]}}, 0(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -101,7 +101,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) { define void @f7(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f7: ; CHECK: algf {{%r[0-5]}}, -4(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -117,7 +117,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) { define void @f8(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f8: ; CHECK: algf {{%r[0-5]}}, -524288(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 @@ -135,7 +135,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) { ; CHECK-LABEL: f9: ; CHECK: agfi %r3, -524292 ; CHECK: algf {{%r[0-5]}}, 0(%r3) -; CHECK: alcgr +; CHECK: alcg ; CHECK: br %r14 %a = load i128 *%aptr %xor = xor i128 %a, 127 |